The DUROC project sets clear and measurable main objectives to reach a TRL 4 from TRL 2 as follows in 2 years:

  • Specifiy and design the next generation of ultra-programmable SoC (ULTRA7) taking benefit of leasson learnt from DAHLIA project (TRL 2)
  • Introduce the ARM 73 processor for very high performance processing specificly designed for advanced process node
  • Validate the SoC on a rad-hard demonstrator in 7nm FinFET technology from TSMC (TRL 4)
  • Validate reliability and radiation hardening performance of 7nm FinFET (TRL 4)
  • Propose a strategy and development plan up to flight model for the next ultra-reprogrammable SoC (ULTRA7)
  • Define the right approach for future SiP use in space applications

At the end of the project, Europe will have all required technical information to be in a position to develop multiple components (SoC FPGA, ASIC etc) on 7nm FinFET which will be the most advanced process node for space. DUROC will bring Europe to an unprecedented leadership position in VLSI electronic for space. DUROC will be the first critial step to develop the next generation of ultra-reprogrammable SoC after NG-ULTRA. The ULTRA 7 will target the following objectives:

  • MPSoC ARM A73 64-bit processor scalability combining ARM R52 real-time control
  • More than 35 000 DMIPS (Millions Instructions per Second)
  • Radiation hardening reliability meeting space payload and platform applications requirements

The following block diagram gives a first overview of potential future ULTRA 7 component. It will be a breaktrough component for space filling the gap with commercial FPGA state of the art. It will keep the NG-ULTRA ARM R52 architecture to keep full design cohenrecy between the two components. In addition, the ULTRA 7 will introduce a high performance quad core processor. The ULTRA 7 block diagram is described below. The objective is really to leverage existing development done on NG-ULTRA and add more processing performance with an ARM A73. DUROC will specify in details the ULTRA 7 and lesson learnt from NG-ULTRA already gives an excellent starting point.On advanced process nodes like 7nm, it will be difficult to develop full SoC as some analog IPS (ADC and DAC etc) will be difficult to port. SiP could be a very efficient approach to mix different chips in the same package to avoid complex and unnecessary IPs portage. SiP also offers very good chip to chip speed connection compared to normal PCB design.

Expected impacts

DUROC will have the following impacts:

  • Reduce the dependence on critical technologies and capabilities from outside Europe for future space applications by providing an ITAR free advanced rad-hard FPGA
  • Develop or regain in the mid-term the European capacity to operate independently in space with access to new generation of rad-hard FPGA beyond current state of the art
  • Enhance the technical capabilities and overall competitiveness of European space industry satellite vendors on the worldwide market by giving prime access to exportation restriction free high performance technologies
  • Work package dedicated to the development of a commercial evaluation of the technology with a full range of recurring products. The future rad-hard FPGA will be available in space qualified package and commercial package with a clear pricing strategy to maximise product dissemination outside space markets
  • Improve the overall European space technology landscape and complement the activities of European and national space programmes. DUROC is clearly set up to complement the ongoing ESA/CNES BRAVE project
  • DUROC will have clear social and environmental impacts by offering a very versatile technology able to meet multiple applications in various markets with the same device. It will also facilitate SMEs access to advance space applications